Solid state memories play a very important role in today's information society, and they are widely used in our daily used electronic products. Conventional memories are mainly DRAMs and flash memories. With the increasing development of the semiconductor industry, a device size becomes smaller and thus the memories are approaching their physical limits. Particularly, after entering into a 22 nm technical node, the memories cannot meet the requirement of development. RRAMs become a powerful competitor among the next generation memories due to advantages such as simple structure, high density integration, low preparation temperature, compatibility with CMOS back end processes, high operation speed, low power consumption and so on. For the high density storage of RRAMs, people tend to use a crossing array structure to integrate, so that a very high density three-dimensional storage of the resistive memory can be achieved.
FIG. 1 illustrates a conventional crossing array structure, in which M bottom electrodes 13 (bit lines) parallel to each other and N top electrodes 11 (word lines) parallel to each other are perpendicularly crossed. At each crossing point, a RRAM memory cell 12 is disposed. FIG. 2 is a schematic diagram of a conventional RRAM memory cell. The RRAM memory cell includes a metal upper electrode 21, a resistive material layer 22 and a metal lower electrode 23. The RRAM memory cell has a following operation principle: in an initial state, the resistive material layer appears a high resistance state; when a voltage between the two electrodes is reached to a certain voltage, a current between the two electrodes increases sharply and the resistive material layer becomes a low resistance state, the voltage at this moment being referred to Vset; when the applied voltage becomes a predetermined value, the current between the two electrodes drops rapidly, the voltage at this moment being referred to Vreset. As such, the RRAM memory cell has two information storage states, i.e., a high resistance state (“0”) and a low resistance state (“1”). Reading a resistance of the memory cell is mainly by reading an amount of a current flowing through the memory cell when applying the same voltage, so as to determine whether the memory cell is in a high resistance state or in a low resistance state. If a memory cell in the crossing array is in a high resistance state while others adjacent thereto are in a low resistance state, a correct reading for the resistance of the memory cell with high resistance may be affected. The reason lies in that, when the memory cell with high resistance is read, an applied voltage may bypass that memory cell and form a sneak current on the memory cells with low resistance, and the sneak current flowing through the memory cells with low resistance is far greater than the current flowing through the memory cell with high resistance. At this time, the current read from the memory cell with high resistance is actually the sneak current flowing through the memory cells with low resistance adjacent thereto. As a result, the memory cell with high resistance may be determined as a memory cell with low resistance, which may result in a misread and error operation. The sneak current in the array limits the further improvement of the integration density of the array. In addition, the sneak current not only causes the misread of the resistance state in the array, but also increases the overall power consumption of the array.
Currently, a 1D1R structure (one diode and one RRAM) is proposed to inhibit the generation of the sneak current in order to solve the above problems. Diodes are mainly classified into silicon-based diodes and metal-oxide-based diodes. However, the silicon-based diodes require a high fabrication temperature, and the metal-oxide-based diodes are prone to transit into the RRAM and thus lose their rectification characteristic. In addition, the diodes have a low drive current which cannot meet the usage requirement of the RRAM. Therefore, there is a need to propose a new structure for suppressing the sneak current.